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EUROPEAN KA-BAND HIGH POWER SOLID STATE TECHNOLOGY FOR ACTIVE ANTENNAS (ARTES AT 5C.414)

on 27 March 2020

ESA Open Invitation to Tender AO10215
Open Date: 24/03/2020
Closing Date: 15/07/2020 13:00:00

Status: ISSUED
Reference Nr.: 20.1TT.35
Prog. Ref.: CC-AT 4.0.1
Budget Ref.: E/0534-01G - CC-AT 4.0.1
Special Prov.: BE+DK+FR+DE+IT+NL+ES+SE+CH+GB+IE+AT+NO+FI+PT+GR+LU+CZ+RO+CA+HU+PL
Tender Type: C
Price Range: > 500 KEURO
Products: Satellites & Probes / RF / Microwave Communication (Platform and Payloads) / "Communication - BB (Antennas excluded)" / Analog: Power amplifiers (SSPA, TWTA, ¿)
Technology Domains: RF Systems, Payloads and Technologies / RF Technologies and Equipment / RF Devices
Establishment: ESTEC
Directorate: Directorate Telecom & Integrated Applica
Department: Telecom Technologies,Product&Systems Dep
Division: Technologies and Products Division
Contract Officer: Piesche, Claudia Ria
Industrial Policy Measure: N/A - Not apply
Last Update Date: 24/03/2020
Update Reason: Tender issue

Objective: The objective of this activity is to design, develop and test a 10-20W class Ka-band European Monolithic Microwave Integrated Circuit high power amplifier with improved efficiency as needed for applications in active array antennas. This shall include the development of a European solid state fabrication process. Targeted Improvements: At least a 10-20% improvement of power added efficiency compared with state of the art GaN-on-SiC transistors. Description: Future geostationary and non-geostationary communication satellites will significantly rely on active antennas. Highly efficient solid state power amplifiers are key building blocks ofsuch antennas. Currently, European sources cannot match the performance offered by non-European companies. In addition, some of thenon-European technology is expected to have export restrictions. On the other hand, process modifications, such as the use of low thermally resistive substrates, downscaling of gate length and changes of the device topology, have shown the potential to reach close to50% Power Added Efficiency (PAE) in the lower Ka-band frequency range. In this activity, solid state techniques shall be developed exploring European solid state processes performing better than the state-of-the-art 150 nm gate length GaN processes. A number of processing trials will be carried out to achieve a 10 - 20W class Ka-band amplifier breadboard with close to 50% PAE. This performance shall be demonstrated under continuous wave operation and in line with the derating requirements according to ECSS-Q-ST-30-11C. The developed process must be transferrable for commercialisation.

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